AMD and Intel’s ACE Specification: A Real Step Forward for AI on CPUs, But Not a GPU Replacement

The AI hardware conversation is still dominated by GPUs, tensor cores, HBM, and large accelerator clusters. That is understandable. Large language models, generative AI platforms, and frontier scale training workloads still depend heavily on GPUs and dedicated AI accelerators.

However, there has now been a meaningful development on the CPU side.

AMD and Intel have published the AI Compute Extensions, or ACE, specification for future x86 processors. ACE is designed to improve matrix multiplication performance, scalability, and energy efficiency while integrating with AVX10. Matrix multiplication is one of the core operations behind neural networks and large language models, so this is a significant architectural move for future x86 CPUs. The official ACE whitepaper introduces ACE as a new x86 ISA extension designed to provide matrix acceleration across systems ranging from laptops to data center servers.

This does not suddenly turn future AMD or Intel CPUs into GPU replacements. It does, however, show that CPU vendors are treating AI acceleration as a first class architectural concern rather than relying only on existing vector instructions.

What is ACE?

ACE stands for AI Compute Extensions. It is a new x86 instruction set extension focused on accelerating matrix multiplication.

Traditional CPUs can already run AI workloads using SIMD and vector extensions such as AVX and AVX10. The limitation is that AVX was not originally designed as a dedicated two dimensional matrix engine. ACE changes this by adding matrix oriented execution capability while still reusing the wider AVX10 ecosystem.

According to the official ACE whitepaper, ACE introduces matrix acceleration based on outer product operations designed to work with AVX10. The paper states that an ACE outer product operation can provide a 16× compute density improvement over an equivalent AVX10 multiply accumulate operation while using the same number of input vectors.

In plain English, ACE is about doing more AI relevant mathematical work per instruction, with less overhead, and in a way that can be supported across AMD and Intel x86 CPUs.

Why ACE matters

The most important part of ACE is not only performance. It is standardization.

AI acceleration on CPUs has often been fragmented. Different vendors support different instructions, different optimization paths, and different software approaches. That creates extra work for compiler developers, AI framework maintainers, and software vendors.

ACE gives the x86 ecosystem a shared target.

The official whitepaper says initial software enablement is underway across compilers, debuggers, profilers, deep learning libraries, HPC libraries, NumPy, SciPy, PyTorch, and TensorFlow. It also says AMD and Intel have worked together through the x86 Ecosystem Advisory Group to align and refine ACE as a standardized matrix acceleration feature across the x86 ecosystem.

That matters because AI performance is not just about silicon. The software stack needs to know how to use the hardware efficiently.

For IT teams and infrastructure planners, ACE could eventually mean better CPU side AI inference, faster low precision matrix operations, improved pre-processing and post processing, and more efficient execution of smaller models where using a large GPU may be unnecessary or too costly.

What data types does ACE support?

Modern AI workloads rely heavily on lower precision data types. These can improve throughput, reduce memory bandwidth pressure, and make inference more efficient.

The ACE v1 whitepaper lists native support for INT8, OCP FP8, OCP MXFP8, OCP MXINT8, and BF16. It also describes support for OCP MX block scaling and dedicated format conversion operations for popular OCP MX data types such as FP4, FP6, and FP8.

That is important because AI hardware is increasingly judged by how well it handles the formats modern models actually use.

ACE is therefore not just a generic CPU extension. It is being shaped around the low precision formats that are becoming central to AI inference and model efficiency.

ACE and AMD’s roadmap

This is where the story needs careful wording.

AMD has already shown that future CPU architectures will include more AI focused capabilities. Reporting from Tom’s Hardware on AMD’s CPU roadmap says Zen 6 will bring more AI features, while Zen 7 is expected to introduce a New Matrix Engine with additional AI functionality.

However, there is still no official confirmation that Zen 7’s Matrix Engine is ACE based.

That distinction matters.

ACE is a published x86 specification involving AMD and Intel. Zen 7’s Matrix Engine is an AMD roadmap item. It is tempting to connect the two directly, but AMD has not yet publicly disclosed enough architectural detail to say that Zen 7’s Matrix Engine equals ACE.

The responsible position is this:

ACE makes it more plausible that future x86 CPUs will gain standardised matrix acceleration, but it does not yet confirm the exact implementation AMD will use in Zen 7.

Zen 6 Venice remains the near term AMD CPU story

For AMD’s server roadmap, the more concrete near term development remains EPYC Venice, AMD’s Zen 6 based sixth generation EPYC platform.

AMD has announced that Venice is ramping production on TSMC’s 2nm process technology. AMD describes Venice as part of its next generation cloud, enterprise, HPC, and AI infrastructure roadmap. AMD also says the CPU is becoming more critical as AI workloads scale because it coordinates data movement, networking, storage, security, and system orchestration across the data centre.

Tom’s Hardware reports that Venice is expected to scale up to 256 Zen 6 cores, with up to 16 memory channels delivering 1.6 TB/s of per-socket bandwidth, along with doubled CPU to GPU bandwidth that likely points to PCIe 6.0 support.

That positioning is important. Venice is not being presented as a CPU only replacement for AI accelerators. It is being positioned as a stronger host and orchestration CPU for AI infrastructure.

In other words, the CPU remains essential. It feeds the GPUs, manages the platform, handles storage and networking, and supports the wider system around the accelerators.

The HBM equipped CPU question

One question keeps coming up: will AMD release a mainstream EPYC CPU with HBM for AI workloads?

At the moment, there is still no publicly announced mainstream EPYC CPU with integrated HBM aimed at replacing GPU class AI accelerators.

AMD does have products that combine CPU and GPU technologies in advanced packages. The clearest example is AMD Instinct MI300A, which AMD describes as an accelerated processing unit combining AMD CPU cores and GPUs for HPC and AI workloads. AMD’s MI300A documentation also describes it as combining Zen 4 CPU cores, CDNA3 GPU compute units, and HBM3 memory in a unified package.

MI300A is part of the Instinct accelerator family, not a mainstream EPYC CPU product.

AMD’s public AI infrastructure direction still appears focused on pairing EPYC CPUs with Instinct GPUs and rack scale systems. Tom’s Hardware reports that AMD’s 2027 AI roadmap includes EPYC Verano CPUs, Instinct MI500 series accelerators, and next generation rack scale AI systems.

So, for now, the answer is clear: AMD is strengthening CPUs for AI infrastructure, but GPUs remain the main compute engines for large scale AI.

What ACE does not mean

ACE is important, but it should not be overhyped.

ACE does not mean future x86 CPUs will suddenly compete with high end AI GPUs in frontier model training.

It does not mean AMD has announced GPU class tensor cores inside EPYC.

It does not mean Zen 7’s Matrix Engine has been fully disclosed.

It does not mean HBM equipped mainstream CPUs are replacing GPU clusters.

It does not mean organizations should stop planning around GPUs for demanding AI workloads.

ACE improves the CPU side story. It gives x86 a more AI aware instruction set and a better path for shared software optimization. But the highest performance AI workloads still depend heavily on accelerator memory bandwidth, massive parallelism, specialized matrix engines, and mature GPU software stacks.

Where ACE could make a real difference

ACE could become especially useful where a large GPU is inefficient, unavailable, or unnecessary.

That includes:

Local AI inference on desktops and laptops.
Small and medium model execution.
Edge AI systems.
AI features inside enterprise applications.
Retrieval augmented generation pre-processing.
Embedding workloads.
Low latency CPU side AI tasks.
Data preparation before GPU acceleration.
AI workloads in environments where GPU availability is limited.

This is where CPUs still matter.

Not every AI workload needs a rack of accelerators. Many enterprise AI tasks involve smaller models, search, filtering, data movement, orchestration, and real time decisioning. A more capable AI aware CPU can improve those scenarios.

The bigger picture for AMD

AMD’s strategy is becoming clearer.

On one side, AMD is strengthening EPYC as the CPU foundation for AI infrastructure. Venice is being positioned as a next generation CPU platform for cloud, enterprise, HPC, and AI infrastructure. AMD also says its follow on Verano processor is expected to build on the EPYC platform with advanced memory innovations, including LPDDR, for power constrained workloads.

On the other side, AMD is still relying on Instinct GPUs for the heavy AI compute layer. Its public AI roadmap continues to point toward rack scale systems built around EPYC CPUs, Instinct GPUs, and high speed networking rather than CPU only AI platforms.

ACE fits into this strategy as a CPU side enhancement, not as a replacement for Instinct.

That makes sense. CPUs remain essential in AI systems, but their role is different. They schedule, coordinate, feed, secure, and manage the platform around the accelerators. With ACE, they may also handle more AI inference and matrix heavy tasks directly when that is the better architectural choice.

What to watch next

The next stage will be implementation.

A published specification is not the same thing as shipping silicon. The important things to watch are:

Which AMD and Intel CPUs expose ACE first.
Whether Zen 7’s Matrix Engine is related to ACE.
Compiler support in GCC, LLVM, Intel oneAPI, AOCC, and related toolchains.
Operating system support for any required processor state.
Library support in BLAS, oneDNN, NumPy, SciPy, PyTorch, and TensorFlow.
Real world inference benchmarks.
Power efficiency under sustained AI workloads.
How ACE compares with NPUs and integrated GPUs for small model inference.

The software stack will be just as important as the hardware. Without mature compiler and framework support, ACE will remain interesting on paper but limited in practice.

Bottom line

ACE is the strongest CPU side AI development we have seen so far in the x86 space.

It gives AMD and Intel a shared path toward matrix acceleration, better low precision AI support, and a more consistent programming model for future CPUs, but it does not change the wider AI hardware reality.

GPUs and dedicated accelerators remain the primary engines for frontier LLM training and top tier inference. AMD’s public roadmap still points toward EPYC CPUs working alongside Instinct GPUs, not replacing them.

The best way to understand ACE is this: it makes CPUs better AI participants. It does not make them the whole AI platform.

For enterprise AI, that still matters. Better CPU side AI performance can reduce overhead, improve efficiency, support smaller inference workloads, and make AI features more practical across everyday systems, but for large scale model training and serious accelerator class inference, the GPU remains firmly in charge.

Sources